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IBM0418A8ANLAB-5H Datasheet

  • IBM0418A8ANLAB-5H

  • x18 Fast Synchronous SRAM

  • 24頁

  • ETC

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Preliminary
Features
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
鈥?8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
鈥?0.25碌 CMOS technology
鈥?Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
鈥?Single Differential PECL Clock
鈥?+3.3V Power Supply, Ground, 2.5V V
DDQ
鈥?2.5V LVTTL Input and Output levels
鈥?Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
鈥?Latched Outputs
鈥?Common I/O
鈥?30鈩?Drivers
鈥?Asynchronous Output Enable and Power Down
Inputs
鈥?Boundary Scan using limited set of JTAG
1149.1 functions
鈥?Byte Write Capability & Global Write Enable
鈥?7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
IBM0436A4ANLAB, IBM0436A8ANLAB,
IBM0418A4ANLAB, and IBM0418A8ANLAB are
4Mb and 8Mb Synchronous Register-Latch Mode,
high-performance CMOS Static Random Access
Memories (SRAMs). These SRAMs are versatile,
have a wide input/output (I/O) interface, and can
achieve cycle times as short as 4.5ns. Differential K
clocks are used to initiate the read/write operation;
all internal operations are self-timed. At the rising
edge of the K clock, all address, write-enables, sync
select, and data input signals are registered inter-
nally. Data outputs are updated from output regis-
ters off the falling edge of the K clock. An internal
write buffer allows write data to follow one cycle
after addresses and controls. The device is oper-
ated with a single +3.3V power supply and is com-
patible with 2.5V LVTTL I/O interfaces.
crlL3325.03
08/06/2001
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 24

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