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IBM0436A4ACLAA-4F Datasheet

  • IBM0436A4ACLAA-4F

  • x36 Fast Synchronous SRAM

  • 26頁

  • ETC

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IBM0418A4ACLAA
IBM0436A8ACLAA
IBM0418A8ACLAA
IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
鈥?8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
鈥?0.25 Micron CMOS technology
鈥?Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
鈥?Single Differential HSTL Clock
鈥?+3.3V Power Supply, Ground, 2.0 Volt max
V
DDQ,
and 0.85 Volt V
REF
鈥?HSTL Input and Output levels
鈥?Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
鈥?Latched Outputs
鈥?Common I/O
鈥?Asynchronous Output Enable and Power Down
Inputs
鈥?Boundary Scan using limited set of JTAG
1149.1 functions
鈥?Byte Write Capability & Global Write Enable
鈥?7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
鈥?Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAM
S
鈥擨BM0436A4ACLAA,
IBM0436A8ACLAA, IBM0418A4ACLAA, and
IBM0418A8ACLAA鈥攁re Synchronous Register-
Latch Mode, high-performance CMOS Static Ran-
dom Access Memories that are versatile, have wide
I/O, and can achieve 4.2 ns cycle times. Differential
K clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the falling edge of the K clock. An internal
Write buffer allows write data to follow one cycle
after addresses and controls. The device is oper-
ated with a single +3.3V power supply and is com-
patible with HSTL I/O interfaces.
trlh3320.04
01/01
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 26

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