音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

IBM0436A86SQKA-6 Datasheet

  • IBM0436A86SQKA-6

  • x36 Fast Synchronous SRAM

  • 17頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

.
IBM0418A86LQKA
IBM0436A86LQKA
IBM0418A86SQKA
IBM0436A86SQKA
8 Mb Synchronous Communication SRAM
Features
鈥?100% bus utilization at high frequencies
鈥?Optimized control logic for minimum control
signal interface
鈥?CKE to enable or suspend clock operations
鈥?Three chip enable pins (CE, CE2, CE2) for
depth expansion with double cycle deselect
鈥?Single Read/Write control pin (R/W)
鈥?Individual Byte Write controls
鈥?Synchronous Pipeline Mode of Operation with
fully coherent Self-Timed Late-Late-Write
鈥?Sleep mode, for reduced stand-by power
鈥?100-pin TQFP package
鈥?3.3 V (SQKA) or 2.5 V (LQKA) power supply
and I/O
鈥?LVTTL input and output levels
鈥?256K x 36 or 512K x 18 organization
鈥?Registered control inputs, addresses
and data I/O
鈥?Burst feature supports interleaved or linear
burst orders
Description
The IBM0418A86LQKA/SQKA and
IBM0436A8LQKA/SQKA are 8 Mb Synchronous
Pipeline SRAMs specifically optimized for communi-
cation system applications. These SRAMs utilize the
Late-Late-Write protocol and optimized I/O timing
parameters to permit 100% bus utilization for any
sequence of read and write operations. Please con-
sult application notes for an example at:
http://www.chips.ibm.com/techlib/products/com-
mun/appnotes.html. Developers of non-network sys-
tem communication applications should contact
their local IBM representative for a suitability
assessment and SRAM recommendation.
The clock input (CLK) is used to register all synchro-
nous input pins on its rising edge. Synchronous
inputs include clock enable (CKE), chip enable (CE,
CE2 and CE2), cycle start input (ADV/LD), all
addresses (SA), read/write control (R/W), byte write
controls (BWa, BWb, BWc, BWd) and all data inputs
(DQ).
Asynchronous inputs include output enable (OE),
which may be carefully timed to optimally reduce
bus turn-around time, and Sleep enable (ZZ). The
static burst mode pin (MODE) selects between inter-
leaved and linear burst modes and should be tied
high (or left unconnected) for interleaved burst order
(or if Burst Mode is not used), or tied low for linear
burst order.
Read, Write and Deselect cycles (see
Read/Write
Command Truth Table
on page 7) are initiated with
ADV/LD = low. Subsequent Read or Write opera-
tions can load new addresses (ADV/LD = low), or
use the internally generated burst address if
ADV/LD = high (See Burst Sequence Truth Tables
on page 7) based on the initial address that was
loaded.
For write operations, Byte Write inputs (BWa, BWb,
BWc, BWd) are registered each cycle the address is
loaded externally, or advanced from the i burst
counter, data is registered two active cycles later.
Sleep mode is enabled by switching asynchronous
signal ZZ High. When the SRAM is in Sleep mode,
the outputs will go to a High-Z state, and the SRAM
will draw a standby current of I
SB2Z
after a delay of
t
ZZI
. SRAM data will be preserved during Sleep
mode, but any read or write operation that is pend-
ing while entering Sleep mode is not guaranteed. A
recovery time (t
ZZR
) is required before the SRAM
resumes normal operation.
The SRAM operates from a single 3.3 V or 2.5 V
power supply, and supports LVTTL I/O levels.
llwp.03
10/11/2000
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 16

IBM0436A86SQKA-6相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！