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IBM0436A41QLAB-4 Datasheet

  • IBM0436A41QLAB-4

  • x36 Fast Synchronous SRAM

  • 343.52KB

  • 26頁

  • ETC

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IBM0418A81QLAB
IBM0418A41QLAB
IBM0436A81QLAB
IBM0436A41QLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
鈥?8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
鈥?0.25 Micron CMOS technology
鈥?Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
鈥?Single Differential Extended HSTL Clock
鈥?+3.3V Power Supply, Ground, 1.5V V
DDQ
, and
0.75V V
REF
鈥?HSTL Input and Output levels
鈥?Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
鈥?Registered Outputs
鈥?Common I/O
鈥?Asynchronous Output Enable
鈥?Synchronous Power Down Input
鈥?Boundary Scan using limited set of JTAG
1149.1 functions
鈥?Byte Write Capability and Global Write Enable
鈥?7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs鈥擨BM0436A41QLAB,
IBM0418A41QLAB, IBM0418A81QLAB, and
IBM0436A81QLAB鈥攁re Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, have wide I/O,
and can achieve 3.0ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all Addresses, Write-
Enables, Sync Select, and Data Ins are registered
internally. Data Outs are updated from output regis-
ters off the next rising edge of the K clock. An inter-
nal Write buffer allows write data to follow one cycle
after addresses and controls. The chip is operated
with a single +3.3V power supply and is compatible
with HSTL I/O interfaces.
crrh3316.08
12/00
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 26

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