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IBM03644B4CT3B-75A Datasheet

  • IBM03644B4CT3B-75A

  • x4 SDRAM Module

  • 16頁

  • ETC

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Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364404 IBM03644B4
PC133 Synchronous DRAM - 64Mb Revision B
Features
鈥?High Performance:
-75A,
CL=3
f
CK
t
CK
t
AC
t
RP
t
RCD
t
RC
Clock Frequency
Clock Cycle
Clock Access Time
Precharge Time
RAS to CAS Delay
Bank Cycle Time
133
7.5
5.4
20
20
67.5
Units
MHz
ns
ns
ns
ns
ns
鈥?Programmable Wrap: Sequential or Interleave
鈥?Multiple Burst Read with Single Write Option
鈥?Automatic and Controlled Precharge Command
鈥?Data Mask for Read/Write control
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?Standard Power operation
鈥?4096 refresh cycles/64ms
鈥?Random Column Address every CLK (1-N Rule)
鈥?Single 3.3V
鹵
0.3V Power Supply
鈥?LVTTL compatible
鈥?Package: 54-pin 400 mil TSOP-Type II
54-pin 2 High Stack TSOJ
鈥?Single Pulsed RAS Interface
鈥?Fully Synchronous to Positive Clock Edge
鈥?Four Banks controlled by Bank Selects
鈥?Programmable Burst Length: 1, 2, 4, 8,
full-page;
鈥?Programmable CAS Latency: 3
Description
The IBM0364404CT3 is a four-bank 64Mb Synchro-
nous DRAM organized as 4Mbit x 4 I/O x 4 Bank.
IBM03644B4CT3 is a stacked version of the
64Mb, x 4 component.
This datasheet provides timing information for the
133 MHz performance sort for this synchronous
device. For the complete functional description and
timing diagrams refer to the datasheet 19L3264.
46L8543.F46205
7/99
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漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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