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IBM0325404CT3A-75A Datasheet

  • IBM0325404CT3A-75A

  • x4 SDRAM

  • 68頁(yè)

  • ETC

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.
EC Update (-10)
Features
鈥?High Performance:
IBM0325404 IBM0325804
IBM0325164 IBM03254B4
256Mb Synchronous DRAM - Die Revision A
-75A -260, -360, -10,
Units
CL=3 CL=2 CL=3 CL=3
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
1
t
AC
Clock Access Time
2
133
7.5
鈥?/div>
5.4
100
10
鈥?/div>
6
100
10
鈥?/div>
6
100
10
7
9
MHz
ns
ns
ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Note:
1
Terminated load,
2
Unterminated load. See AC Characteristics (page 39).
鈥?Single-pulsed RAS interface
鈥?Fully Synchronous to Positive Clock Edge
鈥?Four Banks controlled by BS0, BS1 (Bank
Selects)
鈥?Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, or 8
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge command
Data Mask for Read/Write control (x4, x8) and
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend mode and Power Down mode
Standard Power operation
8192 Refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Single 3.3V
鹵
0.3V Power Supply
LVTTL compatible
Packages:
- 54-pin 400 mil TSOP-Type II
- 66-pin 400 mil 2-High Stack TSOJ
Description
The IBM0325404, IBM0325804, and IBM0325164
are four bank Synchronous DRAMs organized as
16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and
4Mbit x 16 I/O x 4 Bank, respectively. IBM03254B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data-transfer rates of up to 133 MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM鈥檚 advanced 256Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for Synchronous DRAM products,
both electrically and mechanically. All the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals, and a
command decoder initiates the necessary timings
for each operation. A fifteen-bit address bus accepts
address data in the conventional RAS/CAS multi-
plexing style. Thirteen row addresses (A0-A12) and
two bank select addresses (BS0, BS1) are strobed
with RAS. Eleven column addresses (A0-A9, A11)
plus bank select addresses and A10 are strobed
29L0000.E36980A
7/99
with CAS. Column address A11 is dropped on the
x8 device and column addresses A9 and A11 are
dropped on the x16 device. Access to the lower or
upper DRAM in a stacked device is controlled by
CS0 and CS1.
Prior to any access, the CAS latency, burst length,
and sequence must be programmed into the device
by address inputs A0-A12, BS0, BS1 during a Mode
Register Set cycle. It is also possible to program a
Multiple Burst sequence with single write cycle for
write-through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133 MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous opera-
tion of both decks of a stacked device is allowed,
depending on the operation being done.
Auto Refresh (CBR), and Self Refresh operation are
supported.
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 68

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