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HYS72V32300GR-7.5 Datasheet

  • HYS72V32300GR-7.5

  • x72 SDRAM Module

  • 232.55KB

  • 19頁

  • ETC

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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC133 1 GByte Module
鈥?168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
鈥?One bank 16M
脳
72, 32M x 72 and 64M
脳
72
two bank 128M
脳
72 organization
鈥?Optimized for ECC applications with very low
input capacitances
鈥?JEDEC standard Synchronous DRAMs
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
鈥?Single + 3.3 V (鹵 0.3 V) power supply
鈥?Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?All inputs and outputs are LVTTL compatible
鈥?Serial Presence Detect with E
2
PROM
鈥?Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
鈥?Card Size: 133.35 mm
脳
43.18 mm
脳
3.99/
8.13 mm with Gold contact pads
(JEDEC MO-161)
鈥?These modules all fully compatible with the
current industry standard PC133
specifications
-7.5
f
CK
t
CK
t
AC
鈥?Performance:
Unit
MHz
ns
ns
Clock Frequency (max.) @ CL = 3
Clock Cycle Time (min.) @ CL = 3
Clock Access Time (min.)
CAS Latency = 3
133
7.5
5.4
The HYS 72Vxx3xxGR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) organized as 16M
脳
72, 32M x 72, 64M
脳
72 and 128M
脳
72 high speed memory arrays
designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72 (256Mbyte)
registered DIMM module is available in two versions (12 or 13 row addresses). All control and
address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock
inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed
by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC
board. The DIMMs use a serial presence detects scheme implemented via a serial E
2
PROM using
the 2-pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 133.35 mm long footprint.
Data Book
1
1.00

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