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HYMD525G726S4 Datasheet

  • HYMD525G726S4

  • 256Mx72|2.5V|K/H/L|x36|DDR SDRAM - Registered DIMM 2GB

  • 16頁

  • ETC

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256Mx72 bits
Registered DDR SDRAM DIMM
HYMD525G726(L)S4-K/H/L
DESCRIPTION
Preliminary
Hynix HYMD525G726(L)S4-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix HYMD525G726(L)S4-
K/H/L series consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy
substrate. Hynix HYMD525G726(L)S4-K/H/L series provide a high performance 8-byte interface in 5.25" width form
factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD525G726(L)S4-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD525G726(L)S4-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
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2GB (256M x 72) Registered DDR DIMM based on
stacked 128Mx4 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Error Check Correction (ECC) Capability
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
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Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
Programmable CAS Latency 1.5 / 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD525G726(L)S4-K
HYMD525G726(L)S4-H
HYMD525G726(L)S4-L
V
DD
=2.5V
V
DDQ
=2.5V
Power Supply
Clock Frequency
133MHz (*DDR266A)
133MHz (*DDR266B)
125MHz (*DDR200)
Interface
Form Factor
184pin Registered DIMM
5.25 x 1.7 x 0.15 inch
SSTL_2
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Jul. 02
1

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