鈥?/div>
1.700 (43.18mm) PCB Height
168-Pin Registered DIMM with Double Sided
ECC support
One 0.22碌F and one 0.0022碌F decoupling
capacitors adopted
Serial Presence Detect with Serial EEPROM
Two Register Buffers & one Inverter used (with
PLL)
Supports Flow-through or Register mode by Pin
No. 147 (REGE)
Meets all the other JEDEC specifications
Single 3.3V鹵0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
Auto precharge/precharge all banks by A
10
flag
鈥?Possible to assert random column address every
clock cycle
鈥?Interleaved auto refresh mode
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
鈥?Programmable /CAS latency ; 2,3 clocks
鈥?Support clock suspend/power down mode by
CKE0
鈥?Data mask function by DQM
鈥?Mode register set programming
鈥?Burst termination command
鈥?Self refresh provides minimum power, full internal
refresh control
ORDERING INFORMATION
Part No.
HYM72V64C756T4P-8
HYM72V64C756T4P-P
HYM72V64C756T4P-S
Clock
Frequency
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
4 Banks
8K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.0/Jul.00