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HYM72V64756BT8 Datasheet

  • HYM72V64756BT8

  • 64Mx72|3.3V|P/S|x18|SDR SDRAM - Unbuffered DIMM 512MB

  • 297.50KB

  • 14頁(yè)

  • ETC

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64Mx72bits
PC100 SDRAM Unbuffered DIMM
based on 32Mx8 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V64756B(L)T8 Series
DESCRIPTION
The HYM72V64756B(L)T8 H-series are high speed 3.3-Volt synchronous dynamic RAM Modules composed of eighteen
32Mx8 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy printed
circuit board. One 0.33mF and one 0.1mF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V64756B(L)T8 H-series are gold plated socket type Dual In-line Memory Modules suitable for easy inter-
change and addition of 512M bytes memory. All addresses, data and control inputs are latched on the rising edge of the
master clock input. The data paths are internally pipelined to achieve very high bandwidths.
FEATURES
鈥?1.15 (29.21mm) PCB Height
鈥?168-Pin Unbuffered DIMM with Double Sided
鈥?/div>
One 0.33碌F and one 0.1碌F decoupling capacitors
adopted
鈥?/div>
ECC support
鈥?Serial Presence Detect with Serial EEPROM
鈥?Meets all the other JEDEC specifications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single 3.3V鹵0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles / 64ms
Fully synchronous ; all inputs referenced to posi-
tive edge of system clock
鈥?Dual or Quad internal banks with single pulsed
/RAS
鈥?Auto precharge/precharge all banks by A
10
flag
鈥?Possible to assert random column address every
clock cycle
鈥?Interleaved auto refresh mode
鈥?Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
鈥?Programmable /CAS latency ; 2,3 clocks
鈥?Support clock suspend/power down mode by
CKE0, CKE1
鈥?Data mask function by DQM
鈥?Mode register set programming
鈥?Burst termination command
鈥?Self refresh provides minimum power, full internal
refresh control
ORDERING INFORMATION
Part No.
HYM72V64756BT8-P
HYM72V64756BT8-S
HYM72V64756BLT8-P
HYM72V64756BLT8-S
Clock
Frequency
100MHz
100MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
Normal
SDRAM
Package
Plating
4 Banks
8K
Low Power
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2/Jul. 02
1

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