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HYM5V72A834ASLTHG-50 Datasheet

  • HYM5V72A834ASLTHG-50

  • x72 EDO Page Mode DRAM Module

  • 10頁

  • ETC

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HYM5V72A804A H-Series
Buffered 8Mx72 bit CMOS DRAM MODULE
based on 8Mx8 DRAM, EDO, ECC, 3.3V, 4K/8K-Refresh
DESCRIPTION
The HYM5V72A804A H-Series is a 8Mx72-bit EDO mode CMOS DRAM module consisting of nine 8Mx8
TSOP and 16-bit BiCMOS line driver in TSSOP on a 168 pin glass-epoxy printed circuit board. 0.1碌F and
0.01碌F decoupling capacitors are mounted for each DRAM. The HYM5V72A804AH G-series is gold plated
socket type Dual In-line Memory Module suitable for easy interchange and addition of 64M byte memory.
FEATURES
鈥?/div>
Max. Active Power Dissipation
Speed
50
60
8K
3.60W
2.95W
4K
4.57W
3.92W
鈥?/div>
Single power supply of 3.3V
鹵
10%
鈥?/div>
Read-Modify-Write Capability
鈥?/div>
LVTTL compatible inputs and outputs
鈥?/div>
/CAS-before-/RAS, /RAS-only, Hidden
and Self refresh capability
鈥?/div>
Refresh cycles
tHPC
25ns
30ns
Part No.
HYM5V72A804A H-Series
HYM5V72A834A H-Series
Ref.
4K
8K攏
陋
鈥?/div>
Fast access time and cycle time
Speed
50
60
tRAC
50ns
60ns
tCAC
18ns
20ns
鈥?/div>
168-Pin Buffered DIMM
鈥?/div>
Buffered inputs (except /RAS and DQ)
鈥?/div>
Parallel Presence Detect with PD/ID pin Matrix
鈥?/div>
Extended Data Out Operation
攏 陋
/CAS-before-/RAS refresh, Hidden refresh
mode : 4K cycles / 64ms
PIN DISCRIPTION
/RAS0, /RAS2
/CAS0, /CAS4,
/WE0, /WE2
/OE0, /OE2
A0, B0, A1-A12
A0, B0, A1-A11
DQ0-DQ71
PD1-PD8
/PDE
ID0, ID1
VCC
VSS
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Address Input(8K Product)
Address Input(4K Product)
Data Input / Output
Presence Detect
Presence Detect Enable
ID Bit
Power (+3.3V)
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev.03 / Jun.98
漏1998
Hyundai Semiconductor

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