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HYB39S5121600AT-7 Datasheet

  • HYB39S5121600AT-7

  • 512Mb (32M x 16) PC133 2-2-2 Available Q402

  • 50頁

  • ETC

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HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
512 MBit Synchronous DRAM
Preliminary Datasheet April 鈥?1
鈥?/div>
High Performance:
-6
fCK
tCK3
tAC3
tCK2
tAC2
166
6
5
7.5
5.4
-7
143
7
5.4
7.5
5.4
-7.5
133
7.5
5.4
10
6
-8
125
8
6
10
6
Units
MHz
ns
ns
ns
ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8
碌s)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Synchronous to Positive Clock Edge
0 to 70
擄C
operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
The HYB39S512400/800/160AT(L) are four bank Synchronous DRAM鈥檚 organized as 4 banks x
32MBit x4, 4 banks x 16MBit x8 and 4 banks x 8Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON鈥檚 advanced 0.14
碌m
512MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply. All 512Mbit components are housed in TSOPII-54 packages.
INFINEON Technologies
1
4.01

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