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HYB39S256160AT-8A Datasheet

  • HYB39S256160AT-8A

  • x16 SDRAM

  • 42頁

  • ETC

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HYB 39S256400/800/160AT
256-MBit Synchronous DRAM
256-MBit Synchronous DRAM
Preliminary Datasheet
鈥?High Performance:
鈥?Multiple Burst Read with Single Write
Operation
鈥?Automatic and Controlled Precharge
Command
-7.5
-8
125
8
6
10
6
-8A
125
8
6
12
6
-8B
100
10
6
15
7
Units
MHz
ns
ns
ns
ns
鈥?Data Mask for Read/Write Control (x4, x8)
鈥?Data Mask for Byte Control (x16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Power Down Mode
鈥?8192 Refresh Cycles / 64 ms (7.8
碌s)
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface
鈥?Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
鈥?-7.5 version for PC133 3-3-3 application
-8 parts for PC100 2-2-2 operation
-8A parts for PC100 3-2-2 operation
-8B parts for PC100 3-2-3 operation
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
133
7.5
5.4
10
6
鈥?Fully Synchronous to Positive Clock Edge
鈥?0 to 70
擄C
operating temperature
鈥?Four Banks controlled by BA0 & BA1
鈥?Programmable CAS Latency: 2 & 3
鈥?Programmable Wrap Sequence: Sequential
or Interleave
鈥?Programmable Burst Length: 1, 2, 4, 8
The HYB 39S256400/800/160AT are four bank Synchronous DRAM鈥檚 organized as
4 banks
脳
16 MBit
脳
4, 4 banks
脳
8 MBit
脳
8 and 4 banks
脳
4 Mbit
脳
16 respectively. These
synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated using the Infineon advanced 0.19
碌m
256 MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
鹵
0.3 V power supply and are available in TSOPII packages.
Data Book
1
1.00

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