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HYB39S256400T-10 Datasheet

  • HYB39S256400T-10

  • 256 MBit Synchronous DRAM

  • 56頁(yè)

  • INFINEON   INFINEON

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256 MBit Synchronous DRAM
HYB 39S256400/800/160T
Preliminary Information
鈥?High Performance:
-8
-8B
100
10
6
12
7
-10
100
10
7
15
8
Units
MHz
ns
ns
ns
ns
鈥?Multiple Burst Read with Single Write
Operation
鈥?Automatic and Controlled Precharge
Command
鈥?Data Mask for Read/Write control (脳 4,
脳
8)
鈥?Data Mask for byte control (脳 16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?8192 refresh cycles/64 ms 7,8
碌
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface versions
鈥?Plastic Packages:
P-TSOPII-54 400mil width (脳 4,
脳
8,
脳
16)
鈥?-8 part for PC100 2-2-2 operation
-8B part for PC100 3-2-3 operation
-10 part for PC66 2-2-2 operation
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
125
8
6
10
6
Fully Synchronous to Positive Clock Edge
0 to 70
擄C
operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3, 4
鈥?Programmable Wrap Sequence: Sequential
or Interleave
鈥?Programmable Burst Length:
1, 2, 4, 8
The HYB 39S256400/800/160T are four bank Synchronous DRAM鈥檚 organized as
4 banks
脳
16 MBit
脳
4, 4 banks
脳
8 MBit
脳
8 and 4 banks
脳
4 MBit
脳
16 respectively. These syn-
chronous devices achieve high speed data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated with SIEMENS鈥?advanced 256 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
鹵
0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01

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