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HYB39S16800CT-10 Datasheet

  • HYB39S16800CT-10

  • 16 MBit Synchronous DRAM

  • 19頁

  • INFINEON   INFINEON

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16 MBit Synchronous DRAM
HYB 39S16400/800/160CT-8/-10
鈥?High Performance:
-8
-10
100
10
7
12
8
Units
MHz
ns
ns
ns
ns
f
CK(MAX.)
t
CK3
t
AC3
t
CK2
t
AC2
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
125
8
6
10
6
鈥?Multiple Burst Read with Single Write
Operation
鈥?Automatic and Controlled Precharge
Command
鈥?Data Mask for Read/Write control
鈥?Dual Data Mask for byte control (脳 16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?4096 refresh cycles/64 ms
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface
鈥?Plastic Packages:
P-TSOPI-44 400mil width (脳 4,
脳
8)
P-TSOPII-50 400mil width (脳 16 )
鈥?-8 version for PC100 applications
Fully Synchronous to Positive Clock Edge
0 to 70
擄C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence:
Sequential or Interleave
鈥?Programmable Burst Length: 1, 2, 4, 8
鈥?Full page (optional) for sequencial wrap
around
The HYB39S16400/800/160CT are dual bank Synchronous DRAM鈥檚 based on SIEMENS 0.25
碌m
process and organized as 2 banks
脳
2 MBit
脳
4, 2 banks
脳
1 MBit
脳
8 and 2 banks
脳
512 kbit
脳
16 respectively. These synchronous devices achieve high speed data transfer rates up to 125
MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output
data to a system clock. The chip is fabricated with SIEMENS鈥?advanced 16 MBit DRAM process
technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to
occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up
to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V
鹵
0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
1998-10-01

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