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HYB39S16800BT-10 Datasheet

  • HYB39S16800BT-10

  • 16 MBit Synchronous DRAM

  • 64頁

  • INFINEON   INFINEON

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HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
16 MBit Synchronous DRAM
Advanced Information
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High Performance:
-8
fCK(max.)
tCK3
tAC3
tCK2
tAC2
125
8
6
10
6
-10
100
10
7
13.3
8
Units
MHz
ns
ns
ns
ns
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Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control (x4, x8)
Dual Data Mask for byte control ( x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPI-44 400mil width ( x4, x8 )
P-TSOPII -50 400 mil width ( x 16 )
-8 version for PC100 applications
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Fully Synchronous to Positive Clock Edge
0 to 70
擄C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
full page(optional) for sequencial wrap
around
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The HYB39S16400/800/160BT are dual bank Synchronous DRAM鈥?based on the die revisions 鈥?鈥?/div>
s
D,
& 鈥?and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16
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respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS鈥檃dvanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
4.98

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