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HYB39S16320TQ-6 Datasheet

  • HYB39S16320TQ-6

  • Special Mode Registers Two color registers Burst Read with S...

  • 70頁

  • INFINEON   INFINEON

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Overview
HYB 39S13620TQ-6/-7/-8
鈥?High Performance:
-6
-7
125
2
8
5.5
-7
125
3
7
5.5
-8
125
3
8
6
Units
MHz
鈭?/div>
ns
ns
鈥?Special Mode Registers
鈥?Two color registers
鈥?Burst Read with Single Write Operation
鈥?Block Write and Write-per-Bit Capability
鈥?Byte controlled by DQM0-3
鈥?Auto Precharge and Auto Refresh Modes
鈥?Suspend Mode and Power Down Mode
鈥?2k refresh cycles/32 ms
鈥?/div>
t
AC
= 5 ns
鈥?/div>
t
SETUP
/
t
HOLD
= 2 ns/1 ns
鈥?Latency 2 @ 125 MHz
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL compatible inputs and outputs
f
CK
latency
166
3
6
5.5
t
CK3
t
AC3
鈥?Single Pulsed RAS Interface
鈥?Programmable CAS Latency: 2, 3
鈥?Fully Synchronous to Positive Clock Edge
鈥?Programmable Wrap Sequence:
Sequential or Interleave
鈥?/div>
Programmable Burst Length:
1, 2, 4, 8 and full page for sequential
1, 2, 4, 8 for interleave
The HYB 39S163200TQ are dual bank Synchronous Graphics DRAM鈥檚 (SGRAM) organized as
2 banks
脳
256 Kbit
脳
32 with built-in graphics features. These synchronous devices achieve high
speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with an
advanced 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM
products, both electrically and mechanically.
RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each
externally applied clock. Internal chip operating modes are defined by combinations of these
signals. A ten bit address bus accepts address data in the conventional RAS/CAS multiplexing
style. Ten row address bits (A0 - A9) and a bank select BA are strobed with RAS. Column address
bits plus a bank select are strobed with CAS.
Prior to any access operation, the CAS latency, burst length and burst sequence must be
programmed into the device by address inputs during a mode register set cycle. An Auto Precharge
function may be enabled to provide a self-timed row precharge. This is initiated at the end of the
burst sequence. In addition, it features the write per bit, the block write and the masked block write
Semiconductor Group
1
1998-10-01

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