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HYB39S128160CT-7.5 Datasheet

  • HYB39S128160CT-7.5

  • 128-MBit Synchronous DRAM

  • 451.55KB

  • 51頁

  • INFINEON   INFINEON

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HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
128-MBit Synchronous DRAM
鈥?High Performance:
-7
-7.5
133
7.5
5.4
10
6
-8
125
8
6
10
6
Units
MHz
ns
ns
ns
ns
鈥?Multiple Burst Read with Single Write
Operation
鈥?Automatic and Controlled Precharge
Command
鈥?Data Mask for Read/Write Control (x4, x8)
鈥?Data Mask for byte control (x16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Power Down and Clock Suspend Mode
鈥?4096 Refresh Cycles / 64 ms
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
143
7
5.4
7.5
5.4
鈥?Single Pulsed RAS Interface
鈥?Fully Synchronous to Positive Clock Edge
鈥?0 to 70
擄
C operating temperature
鈥?Four Banks controlled by BA0 & BA1
鈥?Programmable CAS Latency: 2, 3
鈥?Programmable Wrap Sequence: Sequential
or Interleave
鈥?Programmable Burst Length:
1, 2, 4, 8 and full page
鈥?Random Column Address every CLK
(1-N Rule)
鈥?Single 3.3 V
鹵
0.3 V Power Supply
鈥?LVTTL Interface
鈥?Plastic Packages:
P-TSOPII-54 400mil x 875 mil width
(x4, x8, x16)
鈥?-7
for PC 133 2-2-2 applications
-7.5 for PC 133 3-3-3 applications
-8
for PC100 2-2-2 applications
The HYB 39S128400/800/160CT are four bank Synchronous DRAM鈥檚 organized as 4
banks
脳
8MBit x4, 4 banks
脳
4MBit x8 and 4 banks
脳
2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.17 micron process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
鹵
0.3 V power supply and are available in TSOPII packages.
INFINEON Technologies
1
9.01

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