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Low Power dissipation
max. 450 mW active (-50 version)
max. 378 mW active (-60 version)
max. 306 mW active (-70 version)
Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
Output unlatched at cycle end allows two-
dimensional chip selection
Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and fast page mode
capability
2 CAS / 1 WE control
Self Refresh (L-Version)
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms
Low Power Version only
Plastic Packages:
P-SOJ-40-1 400mil width
The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include Self Refresh (L-
Version), single + 3.3 V (鹵 0.3 V) power supply, direct interfacing with high performance logic
device families.
Semiconductor Group
1
7.96