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HY64UD16162M-E Datasheet

  • HY64UD16162M-E

  • 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

  • 350.27KB

  • 11頁

  • HYNIX

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HY64UD16162M Series
Document Title
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
1.0
1.1
Initial
Revised
- Change Pin Connection
- Improve tOE from 45ns to 30ns
- Correct State Diagram
1.2
Revised
- Correct Package Dimension
- Change Absolute Maximum Ratings
1.3
Revised
- DC Electrical Characteristics ( I
DPD
,I
CC1
)
- State Diagram
- Power Up Sequence
- Deep Power Down Sequence
- Read/Write Cycle Note
1.4
1.5
Revised
- DC Electrical Characteristics ( ICC1: 3mA - > 5mA)
Revised
- Improve Standby Current I
SB1
from 100uA to 80uA
- Add 70ns Part
- Power Up Sequence
1.6
Revised
- Improve ISB1@70ns 100uA to 85uA
- Improve ISB1@85ns 80uA to 75uA
- Improve ICC2@70ns 30mA to 25mA
- Improve ICC2@85ns 30mA to 20mA
- Improve Ambient Temperature C/E to E/I
(0擄C~85擄C/-25擄C~85擄C
鈫?/div>
-25擄C~85擄C/-40擄C~85擄C)
- Improve Maximum Absolute Ratings
(Vdd : -0.3V to 3.3V
鈫?/div>
-0.3V to 3.6V)
- Improve tOE@85ns 30ns to 20ns
1.7
Revised
- Pin Description
- Power Up & Deep Power Down Exit Sequence
Mar. 11. 鈥?02
Final
Feb. 27. 鈥?02
Preliminary
Dec. 20. 鈥?01
Preliminary
Nov. 14. 鈥?01
Preliminary
Oct. 07. 鈥?01
Preliminary
Jul.18. 鈥?01
Preliminary
Draft Date
Jan. 04. 鈥?01
Jul. 03. 鈥?01
Remark
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.7
March. 2002
1

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