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HY628100ALLG Datasheet

  • HY628100ALLG

  • 128Kx8bit CMOS SRAM

  • 130.40KB

  • 9頁

  • HYNIX

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HY628100A Series
128Kx8bit CMOS SRAM
DESCRIPTION
The HY628100A is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100A uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
Product
Voltage
Speed
Operation
No
(V)
(ns)
Current(mA)
HY628100A
5.0
55/70/85
10
Comment : 50ns is available with 30pF test load.
FEATURES
鈥?/div>
Fully static operation and Tri-state output
鈥?/div>
TTL compatible inputs and outputs
鈥?/div>
Battery backup(L/LL-part)
- 2.0V(min) data retention
鈥?/div>
Standard pin configuration
- 32pin 525mil SOP
- 32pin 8x20mm TSOP-I(Standard)
Standby Current(uA)
L
LL
1mA
100
20
Temperature
(擄C)
0~70
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A13
/WE
CS2
A15
Vcc
NC
A16
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
32
30
29
28
27
26
25
24
22
21
20
19
18
17
/OE
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ1
A0
A1
A2
A3
SOP
TSOP-I(Standard)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
BLOCK DIAGRAM
SENSE AMP
A0
ADD INPUT BUFFER
COLUMN DECODER
ROW DECODER
I/O1
OUTPUT BUFFER
I/O8
A16
CONTROL
LOGIC
/CS1
CS2
/OE
/WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 /Feb.99
Hyundai Semiconductor
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