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HY57V653220BTC-7I Datasheet

  • HY57V653220BTC-7I

  • x32 SDRAM

  • 11頁

  • ETC

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HY57V653220B
4 Banks x 512K x 32Bit Synchronous DRAM
D E S C R IP T IO N
The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the
524,288x32.
H Y 5 7 V 6 5 3 2 2 0 B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles
initiated
by
a
single
control
command
(Burst
length
of
1,2,4,8
or
full
page),
and
the
burst
count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
Mobile applications
which require low power consumption and extended temperature range. HY57V653220B is organized as 4banks of
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
- 1, 2, 4, 8 or full page for Sequential Burst
鈥?/div>
All inputs and outputs referenced to positive edge of
system clock
鈥?/div>
鈥?/div>
Data mask function by DQM0,1,2 and 3
Internal four banks operation
鈥?/div>
鈥?/div>
- 1, 2, 4 or 8 for Interleave Burst
Programmable C A S Latency ; 2, 3 Clocks
Burst Read Single Write operation
鈥?/div>
鈥?/div>
鈥?/div>
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
O R D E R IN G IN F O R M A T IO N
Part No.
HY57V653220BTC-6I
H Y 5 7 V 6 5 3 2 2 0 B T C -7 I
HY57V653220BTC-10I
HY57V653220BLTC-6I
HY57V653220BLTC-7I
HY57V653220BLTC-10I
Clock Frequency
166MHz
14 3 M H z
100MHz
Power
Organization
Interface
Package
Normal
166MHz
143MHz
100MHz
4Banks x 512Kbits
x32
LVTTL
400mil 86pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6/Aug.01

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