This family is a 1M bit dynamic RAM organized 1,048,576 x 1-bit configuration with Fast Page mode CMOS
DRAMs. Fast Page mode offers high speed of random access memory within the same row. The circuit and process design
allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns)
and power consumption (Normal or Low power). Hyundai鈥檚 advanced circuit design and process technology allow this
device to achieve high bandwidth, low power consumption and high reliability.
FEATURES
鷗
Fast Page Mode operation
鷗
Read-modify-write Capability
鷗
TTL compatible inputs and outputs
鷗
/CAS-before-/RAS, /RAS-only, Hidden and
Self refresh capability
鷗
Max. Active power dissipation
Speed
60
70
80
鷗
Refresh cycle
Part number
HY531000A
Refresh
512
Normal
8ms
L-part
64ms
Power
467mW
412mW
357mW
鷗
JEDEC standard pinout
鷗
20/26-pin SOJ (300mil)
鷗
Single power supply of 5V
鹵
10%
鷗
Early Write or output enable controlled write
鷗
Fast access time and cycle time
Speed
60
70
80
tRAC
60ns
70ns
80ns
tCAC
15ns
20ns
20ns
tPC
40ns
40ns
45ns
ORDERING INFORMATION
Part Name
HY531000AJ
HY531000ALJ
*L : Low power
Refresh
512
512
Power
Package
20/26Pin SOJ
L-part
20/26Pin SOJ
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of
circuits described. No patent licences are implied
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