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HY512260

128Kx16, CMOS DRAM with /2CAS

DESCRIPTION

This family is a 2M bit dynamic RAM organized 131,072 x 16-bit configuration with CMOS DRAMs. The circuit and process

design allow this device to achieve high performance and low power dissipation. Independent read and write of upper and

lower byte is controlled by 2 separate CAS inputs. Optional features are access time(50, 60 or 70ns) and power onsumption

(Normal or Low power with self refresh). Hyundai鈥檚 advanced circuit design and process technology allow this device to

achieve high bandwidth, low power consumption and high reliability.

FEATURES

鷗

Fast page mode operation

鷗

Read-modify-write Capability

鷗

2/CAS inputs for upper and lower byte control

鷗

TTL compatible inputs and outputs

鷗

/CAS-before-/RAS, /RAS-only, Hidden and

Self refresh capability

鷗

Max. Active power dissipation

Speed

50

60

70

鷗

Refresh cycle

Part number

HY512260

Refresh

512

Normal

8ms

SL-part

128ms

Power

605mW

550mW

495mW

鷗

JEDEC standard pinout

鷗

40-pin Plastic SOJ (400mil)

鷗

Single power supply of 5V

鹵

10%

鷗

Early Write or output enable controlled write

鷗

Fast access time and cycle time

Speed

50

60

70

tRAC

50ns

60ns

70ns

tCAC

15ns

15ns

20ns

tPC

35ns

40ns

45ns

ORDERING INFORMATION

Part Name

HY512260JC

HY512260LJC

HY512260SLJC

*SL : Low power with self refresh

Refresh

512

512

512

Power

Package

40Pin SOJ

L-part

SL-part

40Pin SOJ

40Pin SOJ

This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of

circuits described. No patent licences are implied

Hyundai Semiconductor

Rev.10 / Jan.97

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