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HY29LV160BT-12 Datasheet

  • HY29LV160BT-12

  • 16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory

  • 48頁(yè)

  • HYNIX

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HY29LV160
16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory
KEY FEATURES
n
Single Power Supply Operation
鈥?Read, program and erase operations from
2.7 to 3.6 volts
鈥?Ideal for battery-powered applications
High Performance
鈥?70, 80, 90 and 120 ns access time
versions
Ultra-low Power Consumption (Typical
Values At 5 Mhz)
鈥?Automatic sleep mode current: 1 碌A(chǔ)
鈥?Standby mode current: 1 碌A(chǔ)
鈥?Read current: 9 mA
鈥?Program/erase current: 20 mA
Flexible Sector Architecture:
鈥?One 16 KB, two 8 KB, one 32 KB and
thirty-one 64 KB sectors in byte mode
鈥?One 8 KW, two 4 KW, one 16 KW and
thirty-one 32 KW sectors in word mode
鈥?Top or bottom boot block configurations
available
Sector Protection
鈥?Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
鈥?Sectors lockable in-system or via
programming equipment
鈥?Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
Fast Program and Erase Times
鈥?Sector erase time: 0.25 sec typical for
each sector
鈥?Chip erase time: 8 sec typical
鈥?Byte program time: 9
碌s
typical
Unlock Bypass Program Command
鈥?Reduces programming time when issuing
multiple program command sequences
Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
Erase Suspend/Erase Resume
鈥?Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
鈥?Erase Resume can then be invoked to
complete suspended erasure
Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
n
100,000 Write Cycles per Sector Minimum
n
Data# Polling and Toggle Bits
鈥?Provide software confirmation of
completion of program and erase
operations
Ready/Busy# Pin
鈥?Provides hardware confirmation of
completion of program and erase
operations
Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
Compliant With Common Flash Memory
Interface (CFI) Specification
鈥?Flash device parameters stored directly
on the device
鈥?Allows software driver to identify and use
a variety of different current and future
Flash products
Compatible With JEDEC standards
鈥?Pinout and software compatible with
single-power supply Flash devices
鈥?Superior inadvertent write protection
Space Efficient Packaging
鈥?48-pin TSOP and 48-ball FBGA packages
n
n
n
n
n
n
n
n
n
n
LOGIC DIAGRAM
20
A[19:0]
DQ[7:0]
7
CE#
OE#
WE#
RESET#
BYTE#
DQ[14:8]
DQ15/A-1
RY/BY#
8
n
n
n
n
Preliminary
Revision 1.2, May 2001

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