HT82J97E
USB Joystick Encoder 8-Bit OTP MCU
Features
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Flexible total solution for applications that combine
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Two 8-bit indirect addressing registers
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One 16-bit programmable timer counter with over-
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
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USB Specification Compliance
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Conforms to USB specification V1.1
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Conforms to USB HID specification V1.1
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Supports 1 Low-speed USB control endpoint and 1
flow interrupt (shared with PA7, vector 0CH)
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One USB interrupt input (vector 04H)
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HALT function and wake-up feature reduce power
consumption
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PA0~PA7 support wake-up function
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Internal Power-On reset (POR)
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Watchdog Timer (WDT)
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20 I/O ports (including 2-PWM output, PC2, PC3)
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2 PWM output (PC2, PC3)
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Can produce PWM frequency range from 23Hz to
interrupt endpoint
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Each endpoint has 8麓8 bytes FIFO
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Integrated USB transceiver
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3.3V regulator output
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External 6MHz or 12MHz ceramic resonator or crys-
tal
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8-bit RISC microcontroller, with 2K麓14 EPROM
23kHz
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Built-in 8-bit Analog-to-Digital Converter, (6-channel
(000H~7FFH)
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96 bytes RAM (20H~7FH)
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6MHz/12MHz internal CPU clock
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4-level stacks
for internal mode (PB0~PB5), 6-channel for external
mode with VHL (PB7) and VRL (PB6))
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20/28-pin SOP package
General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 2K麓14 EPROM and 96 bytes data RAM.
Block Diagram
U S B D + /C L K
U S B D -/D A T A
V 3 3 O
U S B 1 .1
P S 2
B P
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
IN T C
M
U
X
f
S
/4
P A 7 /T M R
T M R 0
T M R 0 C
Y S
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M P
M
U
X
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
S Y S C L K /4
W D T O S C
P A C
In s tr u c tio n
D e c o d e r
A L U
S h ifte r
M U X
P A
P O R T A
P A 0 ~ P A 6
P A 7 /T M R
P B C
T im in g
G e n e ra to r
S T A T U S
P B
A /D
P C C
P C
A C C
P W M
P O R T B
P B 0 /A N 0 ~ P B 5 /A N 5
P B 6 /V R L
P B 7 /V R H
C o n v e rte r
P O R T C
P C 0 ~ P C 1
P C 2 /P W M 1
P C 3 /P W M 2
O S C 2
O S
R
V
V
C 1
E S
D D
S S
Rev. 1.30
1
May 10, 2004