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HSP9520CP Datasheet

  • HSP9520CP

  • Multilevel Pipeline Registers

  • 4頁

  • INTERSIL   INTERSIL

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HSP9520, HSP9521
Data Sheet
May 1999
File Number
2811.5
Multilevel Pipeline Registers
These devices are multilevel pipeline registers implemented
using a low power CMOS process. They are pin for pin
compatible replacements for industry standard multilevel
pipeline registers such as the L29C520 and L29C521. The
HSP9520 and HSP5921 are direct replacements for the
AM29520 and AM29521 and WS59520 and WS59521.
They consist of four 8-bit registers which are dual ported.
They can be con鏗乬ured as a single four level pipeline or a
dual two level pipeline. A single 8-bit input is provided, and
the pipelining con鏗乬uration is determined by the instruction
code input to the I0 and I1 inputs (see instruction control).
The contents of any of the four registers is selectable at the
multiplexed outputs through the use of the S0 and S1
multiplexer control inputs (see register select. The output is 8
bits wide and is three-stated through the use of the OE input.
The HSP9520 and HSP9521 differ only in the way data is
loaded into and between the registers in dual two-level
operation. In the HSP9520 when data is loaded into the 鏗乺st
level the existing data in the 鏗乺st level is moved to the second
level. In the HSP9521 loading the 鏗乺st level simply causes
the current data to be overwritten. Transfer of data to the
second level is achieved using the single four level mode (I1,
I0 = 鈥?鈥?. This instruction also causes the 鏗乺st level to be
loaded. The HOLD instruction (I1, I0 = 鈥?鈥? provides a means
of holding the contents of all registers.
Features
鈥?Four 8-Bit Registers
鈥?Hold, Transfer and Load Instructions
鈥?Single 4-Stage or Dual-2 Stage Pipelining
鈥?All Register Contents Available at Output
鈥?Fully TTL Compatible
鈥?Three-State Outputs
鈥?High Speed, Low Power CMOS
Applications
鈥?Array Processor
鈥?Digital Signal Processor
鈥?A/D Buffer
鈥?Telecommunication
鈥?Byte Wide Shift Register
鈥?Mainframe Computers
Pinout
HSP9520, HSP9521 (SOIC, PDIP)
TOP VIEW
I0 1
I1 2
24 V
CC
23 S0
22 S1
21 Y0
20 Y1
19 Y2
18 Y3
17 Y4
16 Y5
15 Y6
14 Y7
13 OE
Ordering Information
PART NUMBER
HSP9520CP
HSP9520CS
HSP9521CP
HSP9521CS
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
24 Ld PDIP
24 Ld SOIC
24 Ld PDIP
24 Ld SOIC
PKG.
NO.
E24.3
M24.3
E24.3
M24.3
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
CLK 11
GND 12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright 漏 Intersil Corporation 1999

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