HSP50307
December 1996
Burst QPSK Modulator
Description
The HSP50307 is a mixed signal burst QPSK Modulator for
upstream CATV Applications. The HSP50307 demultiplexes
and modulates a serial data stream onto an RF Carrier cen-
tered between 8 and 15MHz. The signal spectrum is shaped
with
偽
= 0.5 root raised cosine (RRC) digital 鏗乴ters. On-chip 鏗乴-
tering limits spurs and harmonics to levels below -35dBc dur-
ing transmissions. The output power level is adjustable over a
40dB range in 1dB steps. The maximum differential output
level is +62dBmV into 75鈩? A transmitter inhibit function dis-
ables the RF output outside the burst interval. The differential
output ampli鏗乪r int7-erfaces to the cable via a transformer.
The Block Diagram of the HSP50307 QPSK Modulator is
shown below. The HSP50307 consists of a digital control
interface, an I/Q generator, a synthesizer, and a quadrature
modulator.
The data clock is derived from the master clock. The
HSP50307 demultiplexes the input data bits into in-phase (I)
and quadrature (Q) data streams. The 鏗乺st bit and subsequent
alternating bits of the burst are in-phase data. The two data
streams are 鏗乴tered, converted from digital to analog, and low
pass 鏗乴tered to produce the baseband I and Q analog signals.
PKG.
NO.
M28.3
Features
鈥?256 KBPS Data Rate and 128 KBPS Baud Rate
鈥?Burst QPSK Modulation
鈥?Programmable Carrier Frequency from 8MHz to
15MHz With a Frequency Step Size of 32kHz
鈥?/div>
偽
= 0.5 Root Raised Cosine (RRC) Filtering For Spec-
trum Shaping
鈥?On-Board Synthesizer
鈥?Programmable Output Level From 22 to 62dBmV in
1dB Steps
鈥?Programmable Charge Pump Current Control
鈥?62dBmV Differential Output Driver for 75鈩?Cable
Applications
鈥?Burst QPSK Modulator
鈥?HSP50307EVAL1 Evaluation Board Is Available
Ordering Information
PART NUMBER
HSP50307SC
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
28 Ld SOIC
The baseband signals are up-converted to RF in the Quadra-
ture Modulation Section. The synthesizer provides the local
oscillator (LO) for the quadrature modulator. The frequency is
programmable via the control interface with a resolution of
32kHz. The output of the quadrature modulator is low pass 鏗乴-
tered to remove harmonic distortion.
Block Diagram
RCLK VCO_IN
VCO_SET PD_OUT
RESET
CCLK
C_EN
CDATA
TX_EN
I
TX_DATA
DEMUX
CONTROL
INTERFACE
SYNTHESIZER
鈥?/div>
QUAD
GEN
QUADRATURE
MODULATOR
鈥?/div>
I/Q GENERATOR
9
8RRC
D/A
LPF
鈥?/div>
MOD_OUT-
+
LPF
PGA
MOD_OUT+
D/A
LPF
TX_EN
Q
9
8RRC
TXCLK
MCLK
/100
IBBIN
QBBOUT
鈥?/div>
Indicates analog circuitry.
MCLK MUST ALWAYS BE PRESENT FOR PROPER OPERATION
IBBOUT
QBBIN
DAC_REF
VCM_REF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
4219
7-68
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