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HSP50210JC-52 Datasheet

  • HSP50210JC-52

  • Digital Costas Loop

  • 49頁(yè)

  • INTERSIL   INTERSIL

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HSP50210
Data Sheet
January 1999
File Number
3652.4
Digital Costas Loop
The Digital Costas Loop (DCL) performs many of the
baseband processing tasks required for the demodulation of
BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
waveforms. These tasks include matched 鏗乴tering, carrier
tracking, symbol synchronization, AGC, and soft decision
slicing. The DCL is designed for use with the HSP50110
Digital Quadrature Tuner to provide a two chip solution for
digital down conversion and demodulation.
The DCL processes the In-phase (I) and quadrature (Q)
components of a baseband signal which have been digitized
to 10 bits. As shown in the block diagram, the main signal
path consists of a complex multiplier, selectable matched
鏗乴ters, gain multipliers, cartesian-to-polar converter, and soft
decision slicer. The complex multiplier mixes the I and Q
inputs with the output of a quadrature NCO. Following the
mix function, selectable matched 鏗乴ters are provided which
perform integrate and dump or root raised cosine 鏗乴tering
(偽 ~ 0.40). The matched 鏗乴ter output is routed to the slicer,
which generates 3-bit soft decisions, and to the cartesian-to-
polar converter, which generates the magnitude and phase
terms required by the AGC and Carrier Tracking Loops.
The PLL system solution is completed by the HSP50210
error detectors and second order Loop Filters that provide
carrier tracking and symbol synchronization signals. In
applications where the DCL is used with the HSP50110,
these control loops are closed through a serial interface
between the two parts. To maintain the demodulator
performance with varying signal power and SNR, an internal
AGC loop is provided to establish an optimal signal level at
the input to the slicer and to the cartesian-to-polar converter.
Features
鈥?Clock Rates Up to 52MHz
鈥?Selectable Matched Filtering with Root Raised Cosine or
Integrate and Dump Filter
鈥?Second Order Carrier and Symbol Tracking Loop
Filters
鈥?Automatic Gain Control (AGC)
鈥?Discriminator for FM/FSK Detection and Discriminator
Aided Acquisition
鈥?Swept Acquisition with Programmable Limits
鈥?Lock Detector
鈥?Data Quality and Signal Level Measurements
鈥?Cartesian to Polar Converter
鈥?8-Bit Microprocessor Control - Status Interface
鈥?Designed to work with the HSP50110 Digital
Quadrature Tuner
鈥?84 Lead PLCC
Applications
鈥?Satellite Receivers and Modems
鈥?BPSK, QPSK, 8-PSK, OQPSK, FSK, AM and FM
Demodulators
鈥?Digital Carrier Tracking
鈥?Related Products: HSP50110 Digital Quadrature Tuner,
D/A Converters HI5721, HI5731, HI5741
鈥?HSP50110/210EVAL Digital Demod Evaluation Board
Block Diagram
CARRIER
TRACK
CONTROL
HI/LO
(COF)
CARRIER ACQ/TRK
LOOP FILTER
NCO
COS SIN
I SER OR
I
IN
(9-0)
SERCLK
OR CLK
Q SER OR
Q
IN
(9-0)
SYMBOL
TRACK
CONTROL
CONTROL/
STATUS
BUS
(SOF)
10
Q
10
I
RRC
FILTER
INTEGRATE/
DUMP
INTEGRATE/
DUMP
8
CARTESIAN
TO
POLAR
8 MAGNITUDE
8
PHASE
3
SLICER
3
Q
I
LOOP
FILTER
CARRIER PHASE
ERROR DETECT
LEVEL
DETECT
DATA PATH MULTIPLEXER
LOCK
DETECT
LKINT
THRESH
A
OUT(9-0)
10
LEVEL
DETECT
8
RRC
FILTER
10
B
OUT(9-0)
SMBLCLK
OEA
OEB
SYMBOL
TRACKING
LOOP FILTER
13
CONTROL
INTERFACE
SYMBOL
PHASE
ERROR
DETECT
3-253
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999

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