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HSP48901JC-30 Datasheet

  • HSP48901JC-30

  • 3 x 3 Image Filter

  • 9頁

  • INTERSIL   INTERSIL

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HSP48901
Data Sheet
May 1999
File Number
2459.5
3 x 3 Image Filter
The Intersil HSP48901 is a high speed 9-Tap FIR Filter
which utilizes 8-bit wide data and coef鏗乧ients. It can be
con鏗乬ured as a one dimensional (1-D) 9-Tap 鏗乴ter for a
variety of signal processing applications, or as a two
dimensional (2-D) 鏗乴ter for image processing. In the 2-D
con鏗乬uration, the device is ideally suited for implementing 3
x 3 kernel convolution. The 30MHz clock rate allows a large
number of image sizes to be processed within the required
frame time for real-time video.
Data is provided to the HSP48901 through the use of
programmable data buffers such as the HSP9500 or any
other Programmable Shift Register. Coef鏗乧ient and pixel
input data are 8-bit signed or unsigned integers, and the
20-bit extended output guarantees no over鏗俹w will occur
during the 鏗乴tering operation.
There are two internal register banks for storing independent
3 x 3 鏗乴ter kernels, thus, facilitating the implementation of
adaptive 鏗乴ters and multiple 鏗乴ter operations on the same
data.
The con鏗乬uration of the HSP48901 Image Filter is controlled
through a standard microprocessor interface and all inputs
and outputs are TTL compatible.
Features
鈥?DC to 30MHz Clock Rate
鈥?Con鏗乬urable for 1-D and 2-D Correlation/Convolution
鈥?Dual Coef鏗乧ient Mask Registers, Switchable in a Single
Clock Cycle
鈥?Two鈥檚 Complement or Unsigned 8-Bit Input Data and
Coef鏗乧ients
鈥?20-Bit Extended Precision Output
鈥?Standard
碌P
Interface
Applications
鈥?Image Filtering
鈥?Edge Detection/Enhancement
鈥?Pattern Matching
鈥?Real Time Video Filters
Ordering Information
PART NUMBER
HSP48901JC-20
HSP48901JC-30
HSP48901GC-20
HSP48901GC-30
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
68 Ld PLCC
68 Ld PLCC
68 Ld PGA
68 Ld PGA
PKG.
NO.
N68.95
N68.95
G68.A
G68.A
Block Diagram
DIN3 (0-7)
DIN2 (0-7)
DIN1 (0-7)
Z
-1
Z
-1
Z
-1
MODE
CIN0-7
FRAME
Z
-1
Z
-1
A0-2
LD
3
ADDRESS
DECODER
INTERNAL
CLOCK
CLK
HOLD
CLOCK
GEN
I
H
G
Z
-1
F
E
D
2:1
Z
-1
Z
-1
Z
-1
C
B
A
MODE
2:1
Z
-1
Z
-1
Z
-1
CONTROL
LOGIC
Z
-1
Z
-1
+
Z
-1
Z
-1
Z
-1
+
Z
-1
+
Z
-1
Z
-1
Z
-1
Z
-1
+
Z
-1
DOUT 0-19
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright 漏 Intersil Corporation 1999

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