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HSP45256JI-25 Datasheet

  • HSP45256JI-25

  • Binary Correlator

  • 157.20KB

  • 23頁

  • INTERSIL   INTERSIL

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HSP45256
Data Sheet
May 1999
File Number
2814.4
Binary Correlator
The Intersil HSP45256 is a high-speed, 256 tap binary
correlator. It can be con鏗乬ured to perform one-dimensional
or two-dimensional correlations of selectable data precision
and length. Multiple HSP45256鈥檚 can be cascaded for
increased correlation length. Unused taps can be masked
out for reduced correlation length.
The correlation array consists of eight 32-tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8-bit input
data with a 1-bit reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
con鏗乬ured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The mask register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
The output of the correlation array (correlation score) feeds
the weight and sum logic, which gives added 鏗俥xibility to the
data format. In addition, an offset register is provided so that
a preprogrammed value can be added to the correlation
score. This result is then passed through a user
programmable delay stage to the cascade summer. The
delay stage simpli鏗乪s the cascading of multiple correlators
by compensating for the latency of previous correlators.
The Binary Correlator is con鏗乬ured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the control and reference registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
Features
鈥?Recon鏗乬urable 256 Stage Binary Correlator
鈥?1-Bit Reference x 1, 2, 4, or 8-Bit Data
鈥?Separate Control and Reference Interfaces
鈥?25.6, 33MHz Versions
鈥?Con鏗乬urable for 1-D and 2-D Operation
鈥?Double Buffered Mask and Reference
鈥?Programmable Output Delay
鈥?Cascadable
鈥?Standard Microprocessor Interface
Applications
鈥?Radar/Sonar
鈥?Spread Spectrum Communications
鈥?Pattern/Character Recognition
- Error Correction Coding
Ordering Information
PART NUMBER
HSP45256JC-25
HSP45256JC-33
HSP45256GC-25
HSP45256GC-33
HSP45256JI-25
HSP45256JI-33
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
84 Ld PLCC
84 Ld PLCC
85 Ld PGA
85 Ld PGA
84 Ld PLCC
84 Ld PLCC
PKG.
NO.
N84.1.15
N84.1.15
G85.A
G85.A
N84.1.15
N84.1.15
Block Diagram
DOUT
DOUT0-7
DIN0-7
DREF0-7
256 TAP
CORRELATION
ARRAY
DREFOUT
CSCORE
WEIGHT
AND SUM
MUX
AUXOUT0-8
DCONT0-7
CONTROL
A0-2
DELAY
CASCADE
SUMMER
CASOUT0-12
CASIN0-12
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999

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