音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

HSP43220JC-15 Datasheet

  • HSP43220JC-15

  • Decimating Digital Filter

  • 193.68KB

  • 19頁(yè)

  • INTERSIL   INTERSIL

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

HSP43220
Data Sheet
February 1999
File Number
2486.7
Decimating Digital Filter
The HSP43220 Decimating Digital Filter is a linear phase
low pass decimation 鏗乴ter which is optimized for 鏗乴tering
narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220 offers a single chip
solution to signal processing applications which have
historically required several boards of ICs. This reduction in
component count results in faster development times as well
as reduction of hardware costs.
The HSP43220 is implemented as a two stage 鏗乴ter
structure. As seen in the block diagram, the 鏗乺st stage is a
high order decimation 鏗乴ter (HDF) which utilizes an ef鏗乧ient
sample rate reduction technique to obtain decimation up to
1024 through a coarse low-pass 鏗乴tering process. The HDF
provides up to 96dB aliasing rejection in the signal pass
band. The second stage consists of a 鏗乶ite impulse
response (FIR) decimation 鏗乴ter structured as a transversal
FIR 鏗乴ter with up to 512 symmetric taps which can implement
鏗乴ters with sharp transition regions. The FIR can perform
further decimation by up to 16 if required while preserving
the 96dB aliasing attenuation obtained by the HDF. The
combined total decimation capability is 16,384.
The HSP43220 accepts 16-bit parallel data in 2鈥檚
complement format at sampling rates up to 33 MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220 also provides the capability to bypass either the
HDF or the FIR for additional 鏗俥xibility.
Features
鈥?Single Chip Narrow Band Filter with up to 96dB
Attenuation
鈥?DC to 33MHz Clock Rate
鈥?16-Bit 2鈥檚 Complement Input
鈥?20-Bit Coef鏗乧ients in FIR
鈥?24-Bit Extended Precision Output
鈥?Programmable Decimation up to a Maximum of 16,384
鈥?Standard 16-Bit Microprocessor Interface
鈥?Filter Design Software Available DECIMATE鈩?/div>
鈥?Up to 512 Taps
Applications
鈥?Very Narrow Band Filters
鈥?Zoom Spectral Analysis
鈥?Channelized Receivers
鈥?Large Sample Rate Converter
Ordering Information
PART NUMBER
HSP43220VC-33
HSP43220JC-15
HSP43220JC-25
HSP43220JC-33
HSP43220GC-25
HSP43220GC-33
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 0
0 to 70
0 to 70
0 to 70
PACKAGE
100 Ld MQFP
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
84 Ld CPGA
84 Ld CPGA
PKG. NO.
Q100.14x20
N84.1.15
N84.1.15
N84.1.15
G84.A
G84.A
DECIMATE
Software Development Tool (This software tool may be
downloaded from our Internet site: http://www.intersil.com)
Block Diagram
DECIMATION UP TO 1024
INPUT CLOCK
DATA INPUT
CONTROL AND COEFFICIENTS
HIGH ORDER
DECIMATION
FILTER
DECIMATION UP TO 16
FIR
DECIMATION
FILTER
FIR CLOCK
24
DATA OUT
DATA READY
16
16
3-194
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
DECIMATE鈩?is a trademark of Intersil Corporation.

HSP43220JC-15相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！