HSP43168
Data Sheet
November 1999
File Number
2808.8
Dual FIR Filter
The HSP43168 Dual FIR Filter consists of two independent
8-tap FIR 鏗乴ters. Each 鏗乴ter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coef鏗乧ients.
The Block Diagram shows two FIR cells each fed by a
separate coef鏗乧ient bank and one of two separate inputs.
The outputs of the FIR cells are either summed or
multiplexed by the MUX/Adder. The compute power in the
FIR Cells can be con鏗乬ured to provide quadrature 鏗乴tering,
complex 鏗乴tering, 2-D convolution, 1-D/2-D correlations, and
interpolating/decimating 鏗乴ters.
The FIR cells take advantage of symmetry in FIR
coef鏗乧ients by pre-adding data samples prior to
multiplication. This allows an 8-tap FIR to be implemented
using only 4 multipliers per 鏗乴ter cell. These cells can be
con鏗乬ured as either a single 16-tap FIR 鏗乴ter or dual 8-tap
FIR 鏗乴ters. Asymmetric 鏗乴tering is also supported.
Decimation of up to 16 is provided to boost the effective number
of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16 x16.
The 鏗俥xibility of the Dual is further enhanced by 32 sets of
user programmable coef鏗乧ients. Coef鏗乧ient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coef鏗乧ient sets further simpli鏗乪s
applications such as polyphase or adaptive 鏗乴tering.
The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
con鏗乬uration of the device is controlled through a standard
microprocessor interface.
Features
鈥?Two Independent 8-Tap FIR Filters Con鏗乬urable as a
Single 16-Tap FIR
鈥?10-Bit Data and Coef鏗乧ients
鈥?On-Board Storage for 32 Programmable Coefficient Sets
鈥?Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit
Data and Coef鏗乧ients
鈥?Programmable Decimation to 16
鈥?Programmable Rounding on Output
鈥?Standard Microprocessor Interface
Applications
鈥?Quadrature, Complex Filtering
鈥?Image Processing
鈥?Polyphase Filtering
鈥?Adaptive Filtering
Ordering Information
PART NUMBER
HSP43168VC-33
HSP43168VC-40
HSP43168VC-45
HSP43168JC-33
HSP43168JC-40
HSP43168JC-45
HSP43168JI-40
HSP43168GC-45
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
0 to 70
PACKAGE
100 Ld MQFP
100 Ld MQFP
100 Ld MQFP
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
84 Ld CPGA
PKG. NO.
Q100.14x20
Q100.14x20
Q100.14x20
N84.1.15
N84.1.15
N84.1.15
N84.1.15
G84.A
Block Diagram
10
CIN0 - 9
A0 - 8
WR
CSEL0 - 4
9
CONTROL/
CONFIGURATION
COEFFICIENT
BANK A
10
INA0 - 9
FIR CELL A
MUX
MUX
COEFFICIENT
BANK B
FIR CELL B
INB0 - 9/
OUT0 - 8
10
MUX /
ADDER
9
OEL
OEH
19
OUT9 - 27
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999