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HPL5331G5C-TRL Datasheet

  • HPL5331G5C-TRL

  • 3A Bus Termination Regulator

  • 20頁

  • ETC

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HPL5331
3A Bus Termination Regulator
Features
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Provide Bi-direction Current
- Sourcing or Sinking Current up to 3A
1.25V/0.9V Output for DDR I/II Applications
Fast Transient Response
High Output Accuracy
- 鹵20mV over Load, VOUT Offset and
Temperature
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Adjustable Output Voltage by External Resistors
Current-Limit Protection
On-Chip Thermal Shutdown
Shutdown for Standby or Suspend Mode
Simple SOP-8, SOP-8-P with thermal pad,
TO-252- 5 and TO-263-5 Packages
General Description (Cont.)
On-chip thermal shutdown provides protection against
any combination of overload that would create ex-
cessive junction temperature. The output voltage of
HPL5331
track the voltage at VREF pin. A resistor
divider connected to VIN, GND and VREF pins is
used to provide a half voltage of VIN to VREF pin. In
addition, an external ceramic capacitor and an open-
drain transistor connected to VREF pin provides soft-
start and shutdown control respectively. Pulling and
holding the VREF to GND shuts off the output. The
output of HPL5331 will be high impedance after being
shut down by VREF or thermal shutdown function.
Pin Configuration
VIN
GND
Applications
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DDR I/II SDRAM Termination
SSTL-2/3 Termination Voltage
Applications Requiring the Regulator with
Bi-direction 3A Current Capability
1
2
3
4
8
7
6
5
VCNTL
VCNTL
VCNTL
VCNTL
VOUT
VREF
VCNTL
GND
VIN
VREF
VOUT
TAB is VCNTL
SOP-8 (Top View)
VIN
TO-252-5 (Top View)
5
4
3
2
1
VOUT
VREF
VCNTL
GND
VIN
1
2
3
4
8
7
6
5
NC
NC
General Description
The HPL5331 linear regulator is designed to provide a
regulated voltage with bi-directional output current for
DDR-SDRAM termination. The HPL5331 integrates
two power transistors to source or sink current up to
3A. It also incorporate current-limit, thermal shutdown
and shutdown control functions into a single chip. Cur-
rent-limit circuit limits the short-circuit current.
GND
VREF
VOUT
TAB is VCNTL
VCNTL
NC
SOP-8-P (Top View)
NC = No internal connection
TO-263-5 (Top View)
= Thermal Pad
(connected to GND plane for better heat
dissipation)
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Copyright HIPAC Semiconductor, Inc.
Rev. A.8 - Oct., 2003
1
www.hipacsemi.com
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2
3
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