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HM64YLB36514 Datasheet

  • HM64YLB36514

  • 16M Synchronous Late Write Fast Static RAM (512-kword 】 36-...

  • 22頁

  • RENESAS

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HM64YLB36514 Series
16M Synchronous Late Write Fast Static RAM
(512-kword
脳
36-bit, Register-Latch Mode)
REJ03C0039-0001Z
Preliminary
Rev.0.10
May.15.2003
Description
The HM64YLB36514 is a synchronous fast static RAM organized as 512-kword
脳
36-bit. It has realized
high speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
鈥?/div>
2.5 V
鹵
5% operation and 1.5 V (V
DDQ
)
鈥?/div>
16M bit density
鈥?/div>
Internal self-timed late write
鈥?/div>
Byte write control (4 byte write selects, one for each 9-bit)
鈥?/div>
Optional
脳18
configuration
鈥?/div>
HSTL compatible I/O
鈥?/div>
Programmable impedance output drivers
鈥?/div>
Differential pseudo-HSTL clock inputs
鈥?/div>
Asynchronous
G
output control
鈥?/div>
Asynchronous sleep mode
鈥?/div>
FC-BGA 119pin package with SRAM JEDEC standard pinout
鈥?/div>
Limited set of boundary scan JTAG IEEE 1149.1 compatible
鈥?/div>
Protocol: Single differential clock register-latch mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology's Sales Dept. regarding specifications.
Rev.0.10, May.15.2003, page 1 of 22

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