HM63921 Series
2048-word
脳
9-bit CMOS Parallel In-Out FIFO Memory
The HM63921 is a first-in, first-out memory that
utilizes a high performance static RAM array with
internal algorithm that controls, monitors and
declares status of the memory by empty flag, full
flag and half-full flag, to prevent data overflow or
underflow.
Expansion logic warrants unlimited expansion
capability in width and depth. Both read and write
are independent from each other and their
corresponding pointers are designed to select the
proper locations out of the entire array serially
without address information to load or unload data.
Data is toggled in and out of the device through the
use of the write enable (
W
) and read enable (
R
)
pins. The device has a read/write cycle time of
30/35/45 ns. Organization of HM63921 provides a
9-bit data bus. The ninth bit could be used for
control or parity for error checking at the option of
the user. The HM63921 is fabricated using the
Hitachi CMOS 1.3 micron technology. The device
is available in DIP and SOJ.
Pin Arrangement
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
(Top view)
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
First-in, first-out dual port memory
2 k
脳
9 organization
Low-power CMOS 1.3 micron technology
Asynchronous and simultaneous read and write
Fully expandable in depth and/or width
Single 5 V power supply
Empty and full warning flags
Half-full flag
Access time: 22/25/35 ns
Package: 300-mil 28-pin plastic DIP package
300-mil 28-pin plastic SOJ package
Ordering Information
Type name
HM63921P-20R
Access time
22 ns
Package
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
300-mil 28-pin
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
plastic DIP
HM63921P-25
25 ns
(DP-28NA)
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
HM63921P-35
35 ns
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
300-mil 28-pin
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
plastic SOJ
HM63921JP-25
25 ns
(CP-28DN)
HM63921JP-20R 22 ns
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
HM63921JP-35
35 ns
鈥撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€撯€?/div>
1
HM63921JP-35相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠(chǎng)商
下載
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC
-
英文版
2048-word x 9-bit CMOS Parallel In-Out FIFO Memory
ETC [ETC]
1
2
