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HM628128 Datasheet

  • HM628128

  • 1 M SRAM (128-kword x 8-bit)

  • 20頁

  • HITACHI

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HM628128D Series
1 M SRAM (128-kword
脳
8-bit)
ADE-203-996 (Z)
Preliminary, Rev. 0.0
Jan. 20, 1999
Description
The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword
脳
8-bit. HM628128D
Series has realized higher density, higher performance and low power consumption by employing Hi-
CMOS process technology. The HM628128D Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP,
standard 32-pin plastic SOP and standard 32-pin plastic TSOPI.
Features
鈥?/div>
Single 5 V supply: 5 V
鹵
10%
鈥?/div>
Access time: 55 ns/70 ns (max)
鈥?/div>
Power dissipation
錚?/div>
Active: 30 mW/MHz (typ)
錚?/div>
Standby: 10
碌W
(typ)
鈥?/div>
Completely static memory.
錚?/div>
No clock or timing strobe required
鈥?/div>
Equal access and cycle times
鈥?/div>
Common data input and output
錚?/div>
Three state output
鈥?/div>
Directly TTL compatible all inputs
鈥?/div>
Battery backup operation
錚?/div>
2 chip selection for battery backup

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