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HM624100HJP-15 Datasheet

  • HM624100HJP-15

  • 4M High Speed SRAM (1-Mword x 4-bit)

  • 13頁

  • HITACHI

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HM624100H Series
4M High Speed SRAM (1-Mword
脳
4-bit)
ADE-203-789D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM624100H is a 4-Mbit high speed static RAM organized 1-Mword
脳
4-bit. It has realized high speed
access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The HM624100H is packaged in 400-mil 32-pin SOJ
for high density surface mounting.
Features
鈥?/div>
Single 5.0 V supply : 5.0 V
鹵
10 %
鈥?/div>
Access time 10/12/15 ns (max)
鈥?/div>
Completely static memory
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
錚?/div>
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
錚?/div>
All inputs and outputs
Operating current : 200/180/160 mA (max)
TTL standby current : 70/60/50 mA (max)
CMOS standby ccurrent : 5 mA (max)
: 1.2 mA (max) (L-version)
Data retension current : 0.8 mA (max) (L-version)
Data retension voltage : 2.0 V (min) (L-version)
Center V
CC
and V
SS
type pinout

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