HM-65642/883
March 1997
8K x 8 Asynchronous
CMOS Static RAM
Description
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simpli鏗乪d by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
Features
鈥?This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
鈥?Full CMOS Design
鈥?Six Transistor Memory Cell
鈥?Low Standby Supply Current . . . . . . . . . . . . . . . .100碌A(chǔ)
鈥?Low Operating Supply Current . . . . . . . . . . . . . . . 20mA
鈥?Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
鈥?Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
鈥?CMOS/TTL Compatible Inputs/Outputs
鈥?JEDEC Approved Pinout
鈥?Equal Cycle and Access Times
鈥?No Clocks or Strobes Required
鈥?Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
鈥?Temperature Range -55
o
C to +125
o
C
鈥?Easy Microprocessor Interfacing
鈥?Dual Chip Enable Control
Ordering Information
PACKAGE
CERDIP
CLCC
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
150ns/75碌A(chǔ)
HM1-65642B/883
HM4-65642B/883
150ns/150碌A(chǔ)
HM1-65642/883
HM4-65642/883
200ns/250碌A(chǔ)
HM1-65642C/883
-
PKG. NO.
F28.6
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VCC
27 W
26 E2
25 A8
24 A9
23 A11
22 G
21 A10
20 E1
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A6
A5
A4
A3
A2
5
6
7
8
9
HM4-65642/883 (CLCC)
TOP VIEW
VCC
A12
NC
NC
A7
E2
W
4
3
2
1
32
31
30
29 A8
28 A9
27 A11
26 NC
25 G
24 A10
23 E1
22 DQ7
21 DQ6
PIN
A
DQ
E1
E2
W
G
NC
GND
VCC
DESCRIPTION
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
Power
A1 10
A0 11
NC 12
DQ0
13
14
DQ1
15 16
DQ2
GND
17
NC
18
DQ3
19
DQ4
20
DQ5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
3004.1
6-220
INTERSIL
1
2
3
4
5
6
7
8
9
