HM-6551/883
March 1997
256 x 4 CMOS RAM
Description
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing ef鏗乧ient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an inde鏗乶ite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Features
鈥?This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
鈥?Low Power Standby . . . . . . . . . . . . . . . . . . . . 50碌W Max
鈥?Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
鈥?Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
鈥?Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
鈥?TTL Compatible Input/Output
鈥?High Output Drive - 1 TTL Load
鈥?Internal Latched Chip Select
鈥?High Noise Immunity
鈥?On-Chip Address Register
鈥?Latched Outputs
鈥?Three-State Output
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
-55
o
C to +125
o
C
220ns
HM-6551B/883
300ns
HM1-6551/883
PKG. NO.
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
PIN
A
E
W
S
D
Q
DESCRIPTION
Address Input
Chip Enable
Write Enable
Chip Select
Data Input
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
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Copyright
漏
Intersil Corporation 1999
File Number
2988.1
6-101
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