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HM-6518/883 Datasheet

  • HM-6518/883

  • 1024 x 1 CMOS RAM

  • 224.46KB

  • 9頁

  • INTERSIL   INTERSIL

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HM-6518/883
March 1997
1024 x 1 CMOS RAM
Description
The HM-6518/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address and data outputs
allowing ef鏗乧ient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6518/883 is a fully static RAM and may be
maintained in any state for an inde鏗乶ite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Features
鈥?This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
鈥?Low Power Standby . . . . . . . . . . . . . . . . . . . . 50碌W Max
鈥?Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
鈥?Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
鈥?Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
鈥?TTL Compatible Input/Output
鈥?High Output Drive - 2 TTL Loads
鈥?High Noise Immunity
鈥?On-Chip Address Register
鈥?Two-Chip Selects for Easy Array Expansion
鈥?Three-State Output
Ordering Information
PACKAGE
CERDIP
TEMP. RANGE
-55
o
C to +125
o
C
PART
NUMBER
HM1-6518/883
PKG. NO.
F18.3
Pinout
HM-6518/883
(CERDIP)
TOP VIEW
S1
E
A0
A1
A2
A3
A4
Q
GND
1
2
3
4
5
6
7
8
9
18 VCC
17 S2
16 D
15 W
14 A9
13 A8
12 A7
11 A6
10 A5
PIN
A
E
W
S
D
Q
DESCRIPTION
Address Input
Chip Enable
Write Enable
Chip Select
Data Input
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
2986.1
6-85

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