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HM-6504/883 Datasheet

  • HM-6504/883

  • 4096 x 1 CMOS RAM

  • 10頁

  • INTERSIL   INTERSIL

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HM-6504/883
March 1997
4096 x 1 CMOS RAM
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing ef鏗乧ient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an inde鏗乶ite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Features
鈥?This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
鈥?Low Power Standby . . . . . . . . . . . . . . . . . . . 125碌W Max
鈥?Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
鈥?Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
鈥?TTL Compatible Input/Output
鈥?Three-State Output
鈥?Standard JEDEC Pinout
鈥?Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
鈥?18 Pin Package for High Density
鈥?On-Chip Address Register
鈥?Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
-55
o
C to +125
o
C
200ns
HM1-6504B/883
300ns
HM1-6504/883
PKG. NO
F18.3
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
A0
A1
A2
A3
A4
A5
Q
W
GND
1
2
3
4
5
6
7
8
9
18 VCC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
PIN
A
E
W
D
Q
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
2993.1
6-134

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