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HDMP-2631B Datasheet

  • HDMP-2631B

  • Telecomm/Datacomm

  • 23頁

  • ETC

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Agilent HDMP-2630B/2631B
2.125/1.0625 GBd Serdes Circuits
Data Sheet
Description
This data sheet describes the
HDMP-2630B/2631B serdes devices
for 2.125 GBd serial data rates.
References to SSTL_2 in the text
will also apply to SSTL_3; however,
there are separate tables and figures
showing voltage values and connec-
tion diagrams for these two logic
families.
The HDMP-2630B/2631B Serdes
are silicon bipolar integrated cir-
cuits in a metallized QFP package.
They provide a low-cost physical
layer solution for 2.125 GBd serial
link interfaces including a complete
Serialize/Deserialize (Serdes) func-
tion with transmit and receive sec-
tions in a single device. The
HDMP-2630B/2631B are also ca-
pable of operating on 1.0625 GBd
serial links. Input pins TX_RATE
and RX_RATE select the data rates
on the transmit and receive sides
respectively.
As shown in Figure 1, the transmit-
ter section accepts 10-bit wide
parallel SSTL_2 data (TX[0:9]) and
a 106.25 MHz SSTL_2 byte clock
(TBC) and serializes them into a
high-speed serial stream. The
parallel data is expected to be
鈥?B/10B鈥?encoded data or equiva-
lent. At the source, TX[0:9] and
TBC switch synchronously with
respect to a 106.25 MHz clock
internal to the sender. New data
are emitted on both edges of
TBC; this is called Double Data
Rate (DDR). The HDMP-2630B/
2631B find a sampling window
between the two edges of TBC to
latch TX[0:9] data into the input
register of the transmitter section
when TX_RATE =1. If TX_RATE
= 0, the user must ensure no
data transitions on the falling
edge of TBC and this edge is used
to latch in parallel data resulting
in a 1.0625 GBd serial stream.
The transmitter section鈥檚 PLL
locks to the 106.25 MHz TBC.
This clock is then multiplied by
20 to generate the 2125 MHz
serial clock for the high-speed
serial outputs. The high speed
outputs are capable of interfacing
directly to copper cables or PCB
traces for electrical transmission
or to a separate fiber optic
module for optical transmission.
Features
鈥?10-bit wide parallel Tx, Rx busses
鈥?106.25 MHz TBC and RBC[0:1]
鈥?Option to set Tx and Rx serial
data rates separately
鈥?Parallel data I/O, clocks and
control compatible with SSTL_2
(HDMP-2630B) or SSTL_3
(HDMP-2631B)
鈥?Differential PECL or LVTTL REFCLK
at 106.25 MHz or 53.125 MHz
鈥?Double data rate transfers
鈥?Source synchronous clocking of
transmit data
鈥?Source centered or source
synchronous clocking of receive
data
鈥?Dual or single receive byte
clocks
鈥?Parallel loopback mode
鈥?Differential BLL serial I/O with
on-chip source termination
鈥?14 mm, 64-pin MQFP package
鈥?Single +3.3V power supply
Applications
鈥?Fibre channel arbitrated loop and
trunks
鈥?Fast serial backplanes
鈥?Clusters
Ordering Information
Part Number
Parallel I/O
HDMP-2630B
SSTL_2
HDMP-2631B
SSTL_3

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