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HD74LVCZ240ATELL Datasheet

  • HD74LVCZ240ATELL

  • Octal Buffers / Line Drivers with 3?state Outputs

  • 9頁

  • RENESAS

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HD74LVCZ240A
Octal Buffers / Line Drivers with 3鈥搒tate Outputs
REJ03D0370鈥?300Z
(Previous ADE-205-229A (Z))
Rev.3.00
Jul. 30, 2004
Description
The HD74LVCZ240A has eight inverter drivers with three state outputs in a 20 pin package. This device is an
inverting buffer and has two active low enables (1G and 2G). Each enable independently controls four buffers.
When V
CC
is between 0 and 1.5 V, the device is in the high impedance state during power up or power down.
Low voltage and high-speed operation is suitable at battery drive product (note type personal computer) and low power
consumption extends the life of a battery for long time operation.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.7 to 5.5 V
All inputs V
IH
(Max) = 5.5 V (@V
CC
= 0 to 5.5 V)
All outputs V
O
(Max) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
High impedance state during power up and power down
Power off disables outputs, permitting live insertion
High output current 鹵24 mA (@V
CC
= 3.0 to 5.5 V)
Ordering Information
Package Type
SOP鈥?0 pin (JEITA)
TSSOP鈥?0 pin
Package Code
FP鈥?0DAV
TTP鈥?0DAV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LVCZ240AFPEL
HD74LVCZ240ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
G
H
L
L
H: High level
L: Low level
X: Immaterial
Z: High impedance
A
X
H
L
Output
Y
Z
L
H
Rev.3.00 Jul. 30, 2004 page 1 of 8

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