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HD74LVC125ATELL Datasheet

  • HD74LVC125ATELL

  • Quad. Bus Buffer Gates with 3-state Outputs

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HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348鈥?400Z
(Previous ADE-205-108C (Z))
Rev.4.00
Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to
be taken high to put the output into the high impedance condition, whereas the device requires the control input to be
low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive
product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
OUT
(Max.) = 5.5 V (@V
CC
= 0 V or output off state)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
High output current 鹵24 mA (@V
CC
= 3.0 V to 5.5 V)
Ordering Information
Package Type
SOP鈥?4 pin (JEITA)
TSSOP鈥?4 pin
Package Code
FP鈥?4DAV
TTP鈥?4DV
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LVC125AFPEL
HD74LVC125ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
C
H
L
L
H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
A
X
L
H
Outputs Y
Z
L
H
Rev.4.00 Jul. 23, 2004 page 1 of 6

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