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HD74LV574A Datasheet

  • HD74LV574A

  • Octal D-type Flip-Flops with 3-state Outputs

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  • RENESAS

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HD74LV574A
Octal D-type Flip-Flops with 3-state Outputs
REJ03D0520鈥?100
Rev.1.00
Feb. 01, 2005
Description
The HD74LV574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D
inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input.
When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again.
When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of
what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation
is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the
battery life.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current 鹵8 mA (@V
CC
= 3.0 V to 3.6 V), 鹵16 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Part Name
HD74LV574AFPEL
HD74LV574ATELL
Package Type
SOP鈥?0 pin (JEITA)
TSSOP鈥?0 pin
Package Code
(Previous Code)
PRSP0020DD鈥揃
(FP鈥?0DAV)
PTSP0020JB鈥揂
(TTP鈥?0DAV)
Package
Abbreviation
FP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
ELL (2,000 pcs/reel)
Function Table
Inputs
OE
H
L
L
L
Note: H: High level
L: Low level
X: Immaterial
Z: High impedance
Q
0
: Output level before the indicated steady state input conditions were established.
CLK
X
鈫?/div>
鈫?/div>
鈫?/div>
D
X
L
H
X
Output Q
Z
L
H
Q
0
Rev.1.00 Feb. 01, 2005 page 1 of 7

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