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HD74LV573ARP Datasheet

  • HD74LV573ARP

  • LATCH|SINGLE|8-BIT|LV-CMOS|SOP|20PIN|PLASTIC

  • 14頁

  • ETC

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HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-279A (Z)
2nd Edition
July 1999
Description
The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied
to the output control input, all outputs go to a high impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for
the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery
life.
Features
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V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current
鹵8
mA (@V
CC
= 3.0 V to 3.6 V),
鹵16
mA (@V
CC
= 4.5 V to 5.5 V)
Function Table
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Output Q
H
L
Q
0
Z
Note: H:High level
L:Low level
X:Immaterial
Z:High impedance
Q
0
:Output level before the indicated steady state input conditions were established

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