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HD74LV4040ATELL Datasheet

  • HD74LV4040ATELL

  • 12-stage Binary Counter

  • 11頁(yè)

  • RENESAS

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HD74LV4040A
12-stage Binary Counter
REJ03D0337鈥?200Z
(Previous ADE-205-282 (Z))
Rev.2.00
Jul. 20, 2004
Description
The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the
input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-
speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current 鹵6 mA (@V
CC
= 3.0 V to 3.6 V), 鹵12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP鈥?6 pin (JEITA)
SOP鈥?6 pin (JEDEC)
TSSOP鈥?6 pin
Package Code
FP鈥?6DAV
FP鈥?6DNV
TTP鈥?6DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV4040AFPEL
HD74LV4040ARPEL
HD74LV4040ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
CLK
鈫?/div>
鈫?/div>
X
Note: H:
L:
X:
鈫?
鈫?
High level
Low level
Immaterial
Low to high transition
High to low transition
CLR
L
L
H
Output
Q
n
Remains unchanged
Changed
All outputs low
Rev.2.00 Jul. 20, 2004 page 1 of 10

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