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HD74LV2GT245AUSE Datasheet

  • HD74LV2GT245AUSE

  • Dual Bus Transceivers with 3?state Outputs / CMOS Logic Leve...

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  • RENESAS

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HD74LV2GT245A
Dual Bus Transceivers with 3鈥搒tate Outputs /
CMOS Logic Level Shifter
REJ03D0153鈥?200Z
(Previous ADE-205-694A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT245A has two buffers with three state output in a 8 pin package. When DIR is high, data
is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs
to the A outputs. The A and B buses are separated by making the enable input (OE) high level. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic鈥搇evel translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
鈥?/div>
The basic gate function is lined up as Renesas uni logic series.
鈥?/div>
Supplied on emboss taping for high-speed automatic mounting.
鈥?/div>
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : 鈥?0 to +85擄C
鈥?/div>
Logic-level translate function
3.0 V CMOS logic
鈫?/div>
5.0 V CMOS logic (@V
CC
= 5.0 V)
1.8 V or 2.5 V CMOS logic
鈫?/div>
3.3 V CMOS logic (@V
CC
= 3.3 V)
鈥?/div>
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V, Output : Z)
鈥?/div>
Output current 鹵6 mA (@V
CC
= 3.0 V to 3.6 V), 鹵12 mA (@V
CC
= 4.5 V to 5.5 V)
鈥?/div>
All the logical input has hysteresis voltage for the slow transition.
鈥?/div>
Ordering Information
Part Name
HD74LV2GT245AUSE
Package Type
SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 9

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