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HD74LV273A Datasheet

  • HD74LV273A

  • Octal D-type Flip-Flops with Clear

  • 81.15KB

  • 10頁

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HD74LV273A
Octal D-type Flip-Flops with Clear
REJ03D0330鈥?300Z
(Previous ADE-205-273A (Z))
Rev.3.00
Jun. 25, 2004
Description
The HD74LV273A has eight edges trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having
the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The
clear input when low sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-
powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
鈥?/div>
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
鈥?/div>
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Output current 鹵6 mA (@V
CC
= 3.0 V to 3.6 V), 鹵12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Part Name
HD74LV273AFPEL
HD74LV273ARPEL
HD74LV273ATELL
Package Type
SOP鈥?0 pin (JEITA)
SOP鈥?0 pin (JEDEC)
TSSOP鈥?0 pin
Package Code
FP鈥?0DAV
FP鈥?0DBV
TTP鈥?0DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
CLR
L
H
H
H
CLK
X
鈫?/div>
鈫?/div>
鈫?/div>
D
X
H
L
X
Output Q
L
H
L
Q
0
Note: H: High level
L: Low level
X: Immaterial
鈫?
Low to high transition
鈫?
High to low transition
Q
0
: Output level before the indicated steady state input conditions were established.
Rev.3.00 Jun. 25, 2004 page 1 of 9

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